Dual-Core Architecture from AMD
The today抯 leader in the dual-core architecture development, just like in many other innovative initiatives, is AMD Company. The processor developer and manufacturer was the first this year to reveal very clear plans concerning dual-core processor architectures and to demonstrate a working prototype system based on a solution like that. Moreover, we have every reason to believe that the first processor with dual-core architecture, which will go into mass production, will be none other but AMD Opteron.
AMD抯 dual-core development program was established long time ago and has been persistently put into life since the very first day. AMD started talking about the upcoming integration of two cores with AMD64 architecture onto a single silicon die back in 1999, when they worked on this particular architecture. This way, we assume that AMD had already kept in mind the peculiarities of the dual-processor architecture when they just started working on their Athlon 64 and Opteron CPUs. That is why they should have no serious problems with setting up the production of dual-core processors.
It is also quite evident that they could have possibly built a dual-core CPU around the Hammer die, since this die already has a fast Hyper-Transport bus, which could serve to connect two processor cores within a single physical package. However, AMD didn抰 go that way. They are going to use more efficient design, which will allow sharing the resources between the two cores in a more efficient way and will ensure their more productive interaction.
Both cores of AMD抯 dual-core CPUs will feature completely independent execution units and cache memory. In other words, each of the two cores within a single processor from AMD will have its own L2 cache, so the company engineers will have to pay special attention to their coherency. However, I don抰 think this is going to become a really serious problem for AMD: MOESI protocol (Modified, Owned, Exclusive, Shared, Invalid) developed in the times of AMD Athlon MP processors can pretty much guarantee proper cache memory coherency not only for different CPUs of an SMP system, but also for different processor cores.
As for shared resources, they include all other units, which are actually performing the North Bridge functions. Among them are dual-port System Request Interface, which actually connects the processor dies within a single silicon, Crossbar Switch, which connects both processor cores with the shared resources, and the resources to be shared between the cores (up to three HyperTransport buses and the memory controller). In other words the dual-core AMD processor will feature individual cache memory for each of the cores, but at the same time will be equipped with only one memory controller, which will be working with both cores simultaneously.
