FB-DIMM ?Another Memory Translator Hub Approaches the Scene

Intel Corp. made it pretty clear at IDF Spring 2005 show that the future of DDR2 and eventually other types of memory, including DDR3 in its platforms is associated with the so-called fully-buffered DIMM concept. There is a reason for that: current DDR2 platforms have sufficient speed scalability, but face issues with density scalability (only 8 ?12GB of memory can be installed per single memory controller), which is why Intel does not introduce DDR2 support for the Intel Itanium 2 platforms that are intended for high-end servers with 16GB or even more memory. As times go by, high-end applications will require even more memory at high-speeds, which is something that conventional types of DDR2 connections do not support really well.

FB-DIMM solves the issue of density scalability easily: the chipsets now have to support a serial bus similar to PCI Express to connect a special hub located on the memory modules. The memory translator hub will then interact with actual memory devices located on the module using a special protocol. Such approach gives two benefits: one is scalability, another is some additional headroom for high-end memory makers to tweak their modules to gain additional performance (since memory chips now do not communicate with chipsets, but only with the hub, there is additional headroom for their tweaking).

But the FB-DIMMs have a disadvantage too: the latency will be stretched significantly over DDR2. A source among the memory makers said the FB-DIMMs will have 30-40 cycles access time, which is similar to the RDRAM. In fact, the FB-DIMM concept was developed by a team headed by Pete McWilliams, an ex-Rambus engineer.