Closer Look at nForce4 SLI (Intel Edition)
Memory Controller
Of course, one of the most interesting parts of the new NVIDIA nForce4 SLI (Intel Edition) chipset is the built-in memory controller. It is especially interesting, because none of the NVIDIA core logic solutions for Athlon 64 platforms has a memory controller: these systems use the memory controller built into the CPU. Therefore, we cannot say yet whether this memory controller implementation in nForce4 SLI (Intel Edition) is good or bad. However, if you remember, the older nForce/nForce2 chipsets for Athlon XP platform boasted efficient work with the memory subsystem as one of their major trumps. It is evident that the memory controller implemented in the new chipset should be at least as good as the memory controllers of the predecessors.
First of all, I would like to point out that the new memory controller of the nForce4 SLI (Intel Edition) chipset was initially intended to support dual-channel DDR2 SDRAM. The SPP of the new chipset doesn抰 support the regular DDR SDRAM at all. Note also, that NVIDIA made its chipset support not only DDR2-533 SDRAM, but also the faster DDR2-667 SDRAM, which has already started appearing in stores. This way the maximum bandwidth of the memory bus working in 128bit dual-channel mode can reach 10.6GB/s, which is a way higher than the maximum processor bus bandwidth even if this bus is clocked at the maximum 1066MHz frequency.
The higher bandwidth of the memory bus compared to the processor bus can be used efficiently by the peripheral devices working with the memory as well as for hardware data prefetch algorithms. In other words, the 揺xcessive?memory bus bandwidth in the nForce4 SLI (Intel Edition) will not be wasted. By the way, this is exactly the reason why the synchronous mode for the FSB and memory bus is not the preferable mode in nForce4 SLI (Intel Edition) chipset.
Like all other dual-channel memory controllers, the controller of nForce4 SLI (Intel Edition) works in the dual-channel 128-bit mode and provides highest performance only if identical DDR2 DIMM modules are installed in pairs. However, even if you have different memory modules installed into your system, the memory controller of NVIDIA nForce4 SLI (Intel Edition) chipset will still be working in the dual-channel mode, although its performance may get slower in this case.
An important feature of the nForce4 SLI (Intel Edition) memory controller is an individual address and command bus for each of the DIMM modules. As a result, each of these busses receives twice as little workload, which in the end allows reducing the memory modules reaction time to controller commands. NVIDIA抯 memory controller supports 1T Memory Timing, which means that the memory modules receive commands and addresses within the same clock cycle when the controller sent them. The chipsets that do not have an individual bus for addresses and commands of each memory module usually have to work with 2T Memory Timing, which is a must once the bus gets loaded heavily. In this mode the memory modules receive addresses and commands only during the next clock cycle after they have been transferred by the controller.
Besides the 1T Memory Timing setting, individual address and command bus for each memory module allowed NVIDIA to give up sending data in packs including eight 64-bit words. The NVIDIA nForce4 SLI (Intel Edition) uses a burst length of 4 and 1T addressing, but other Pentium 4 core logic solutions use a burst length of 8 and 2T
addressing. As a result, the memory controller of the new NVIDIA chipset can transfer twice as many control commands in-between reads as before.
