Another core strength of DFI's engineering prowess is the BIOS and the options available on the nF4 Ultra-D should make any enthusiast salivate. Those that like to tweak their memory in particular will have a field day. The number of memory adjustment options available is almost overwhelming. All of the overclocking settings are stored under the Genie BIOS menu. There are a lot of things that stand out but several in particular will be highlighted. The front side bus is adjustable from 200-465. While a lot of manufacturers have absurdly high FSB values, there are few that can claim that the majority of the FSB range is usable. DFI will be one of those that can make such a claim as will be seen later on.
Voltage adjustments for the CPU is pretty unique. Besides the standard 0.0125 voltage stepping, DFI also has something an additional fine tuner if you will - a multiplier can be applied to the base voltage to fine tune the actual voltage fed to the CPU in even smaller increments. The ranges are listed in the table and with the highest multiplier of 1.36, a whopping 2.108v can be applied to the processor. Voltages are shown on the Genie BIOS page which is good but the functionality could be improved - DFI shows the current voltage setting that was saved. It might be more useful to show the default voltage instead since the set voltage is already shown through the voltage selection menu.
The Genie BIOS is where the magic happens Memory voltage can be cranked up to 4.0v. Because the potential for damage is there, DFI limits the range by default from 2.5v to 3.2v. A jumper on the motherboard has to be set in order to unlock the 3.2-4.0v range. DFI allows for what seems to be every single adjustable option with regards to memory.
The large set of memory dividers is also very welcome as this will allow again for more better fine tuning of the memory when the FSB starts hitting the stratosphere. To help test for memory stability, DFI also has MemTest86+ built in as a BIOS option. With this enabled, after the post, MemTest86+ will launch. No CD requires, all of this is stored on one of the onboard flash memory chips. How cool is that?
In addition to the very impressive voltage range and options, there is also the DFI exclusive, CMOS reloaded. After the initial post screen and boot detection, settings that are bootable are saved to the SEEPROM. The user then has the option of naming and saving this, or any other configuration with the CMOS reloaded configuration. Four save banks are available and at the whim of the user, each of these sets can be loaded.
Here's a not so quick summary of the BIOS settings and values available-
FSB Bus Speed | 200-456 Mhz in 1 Mhz increments |
HyperTransport Ratio | 1-3 in 0.5 steppings 3-5 in integer steppings |
HyperTransport Bandwith | 8/8, 16/8, 8/16, 16/16 |
CPU Multiplier Ratios | 4 to CPU Max in 0.5 steppings |
PCI Express Frequency | 100-145Mhz in 1 Mhz steppings |
CPU Voltage | 0.800-1.550 in 0.0125v steppings; voltage multiplier settings 1.00, 1.04, 1.10, 1.13, 1.23, 1.26, 1.33, 1.36 |
HyperTransport Voltage | 1.20v to 1.50v in 0.1v steppings |
Chipset Voltage | 1.5v to 1.8v in 0.1v steppings |
DRAM Voltage | 2.5v to 4.9v in 0.1v steppings |
Memory Divider | 1:2, 3:5, 2:3, 7:10, 3:4, 5:6, 9:10, 1:1 |
Command Per Clock | On/Off |
CAS Latency Control (TCL) | 1.0-4.5 in 0.5 steppings |
RAS Latency Control (TCL) | 0-7 Bus Clocks |
Min RAS active time (Tras) | 0-15 Bus Clocks |
Row Precharge Time (Trp) | 0-7 Bus Clocks |
le time (Trc) | 7-22 Bus Clocks |
Row Refresh Cycle Time (Trfc) | 9-24 Bus Clocks |
Row to Row Delay (Trrd) | 0-7 Bus Clocks |
Write Recover Time (Twr) | 2-3 Bus Clocks |
Write to Read Delay (Twtr) | 1-2 Bus Clocks |
Read to Write Delay (Trwt) | 1-8 Bus Clocks |
Refresh Period (Tref) | 16-4708 Cycles; varied stepping size |
Write CAS Latency (Twcl) | 1-8 Bus Clocks |
DRAM Bank Interleave | On/Off |
DQS Skew Control | Increase/Decrease Skew |
DQS Skew Value | 0-255 |
DRAM Drive Strength | Level 2-8 |
DRAM Data Drive Strength | Level 1-4 |
Max Async Latency | 1-15ns |
Read Preamble Time | 2-9.5ns in 0.5 ns steppings |
Idle Cycle Limit | 0-256 Cycles; stepping increments are double the previous value |
Dynamic Counter | Enable/Disable |
R/W Queue Bypass | 0,4,8,16 |
Bypass Max | 0-7 |
32 Byte Granularity | 4 or 8 Bursts |