Again, let?s begin with the synthetic benchmarks results showing the memory bus bandwidth and memory subsystem latency:
| ?/td> | FSB=200MHz | FSB=200MHz | FSB=200MHz | FSB=240MHz |
DDR400
(2-2-2-10) | DDR436
(2-3-2-10) | DDR480
(2-3-3-10) | DDR480
(2-3-3-10) |
ScienceMark 2.0,
Memory Bandwidth, MB/s | 5628 | 6098 | 6346 | 6374 |
ScienceMark 2.0,
Memory Latency, cycles | 104 | 96 | 88 | 88 |
ScienceMark 2.0,
Memory Latency, ns | 43.13 | 39.82 | 36.5 | 36.66 |
SiSoft Sandra 2005,
RAM Int Buffered Bandwidth | 6014 | 6353 | 6534 | 6510 |
SiSoft Sandra 2005,
RAM Float Buffered Bandwidth | 5952 | 6268 | 6464 | 6440 |
Synthetic benchmarks show that as the memory frequency increases, so does its bandwidth, and the latency logically goes down. As for the results obtained for the 240MHz memory, they are about the same in both cases: when we have the nominal clock generator frequency of 200MHz and the new 5/4 divider, as well as clock generator overclocked to 240MHz and the common 1/1 divider.
Now let?s take a look at the complex benchmarks:
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