Not so long ago AMD64 processor family with new E core revision appeared in the market. This processor core manufactured with 90nm process using SOI (Silicon on Insulator) and DSL (Dual Stress Liner) technologies got into a few processor product lines. The new E core found its way into several application fields. You can see it in Athlon 64 and Athlon 64 FX processors, where it is known under Venice and San Diego code names, as well as in dual-core Athlon 64 X2 processors, where it is known as Toledo or Manchester. It is also used in AMD Sempron processors where they call it Palermo.

When AMD develops and puts into mass production new processor cores, it aims not only at increasing the working frequencies of their new processors based on these cores, but also at improving their features and specifications. The E core revision appeared another threshold on this way: it provided Athlon 64 processors and their modifications with a number of absolutely new features. One of the most significant enhancements appeared the support of new SSE3 instructions, which has been already implemented in the competitor's solutions since the 90nm Prescott core. Moreover, the integrated memory controller also underwent a few noticeable enhancements.

The tests showed, however, that the new processors cannot benefit that much from the SSE3 instructions support. There are still very few applications nowadays that really do take advantage of these instructions. Besides, the SSE3 instructions set can hardly be called fully-fledged.

Therefore, we decided to pay special attention to the changes introduced in the memory controller integrated into the E core revision of the new AMD processors. Note that in the earlier revisions of its processor cores AMD not only improved the performance of the integrated memory controller, but also expanded its compatibility with various memory modules and their combinations. The D core revision known mostly as Athlon 64 Winchester appeared a certain threshold at this point. First of all, Winchester processors boasted slightly faster memory controller than their predecessors. Secondly, Winchester based processors could work with DDR400 SDRAM memory modules installed into all the four DIMM slots on the mainboard. It looked like the most optimal solution was right there already, however, AMD engineers didn't think so yet. AMD processors based on the E core revision feature an even more enhanced memory controller.

What did the engineers focus on this time? Of course, they again made a few optimizations in order to improve the memory controller performance. The tests of Venice based processors showed that they were faster than their Winchester based counterparts. Besides, the compatibility got even better. AMD processors on E core revision can work normally in the system with memory modules of different capacity and organization, which makes further upgrades a much simpler task for the users. Also, the CPUs based on the new core can also work just fine with four double-sided DDR400 SDRAM DIMMs. Another interesting feature of the new E core revision based CPUs is the new memory frequency dividers they support. This way, new AMD processors have no problems with DDR SDRAM working at frequencies exceeding 400MHz.

Today we are going to take a closer look at some of the above listed peculiarities of the new memory controller implemented in the E core revision, as they certainly deserve our special attention.