Architectural Peculiarities of Dual Core Design
This is a schematic representation of the pipeline and the architecture. The instructions are coming in and they get assigned to the floating point unit or the integer unit. There is also an independent L2 cache and the bus interface. This is what we have today, and everybody is familiar with this.
For the dual core processor everything will be duplicated. It will have two pipelines, two floating point units, two integer units, two caches and two bus interfaces. And these two cores will be put together in one single piece of silicon as a pair
If we look at the Presler, the only difference from the above described scheme will be the availability of two independent cores within the silicon.
And in case of Paxville processor, we will have a shared common bus interface.
Chipset Interface on Dual and Multi Core Platforms
Intel 955/945 Express chipsets will be designed to support new dual core solutions. This is how the whole thing should actually work.
When the operating system boots up it has to know which core is Core 0, the boot strap device, and which core is Core 1. And that?s defined by the way the bus request lines are routed on the sub-straight of the package. So when the processor powers up, the BREQ lines are set appropriately and Core 0 is identified as boot strap device.
Note that contemporary Intel 925 and 915 chipsets do not support dual core, multi-core or multi-processing systems. So if you happen to install the Pentium D processor in one of these older platforms it is not going to work. There will be no power sent to the processor. So, no harm is going to be done to either the board or the processor, and you can take it out and install into the right platform and it will work as expected.
The Dempsy dual-processor platform supports 2 sockets, and as you may notice on the picture below there are two independent bus interfaces.
There are two completely separate trace routing procedures for each socket, because it gives better optimization and more efficient data transfer rates between the two cores and memory. Number of loads on the bus equals three on each bus. If both sockets are assigned to the same bus there will be 5 loads and the bus may not work correctly.
The architecture for the Paxville multi-processor is very similar: there are two sockets per bus, two independent busses on the E8500 chipset, but here it is possible because the bus interface can be shared between the two execution cores.
This bus allows the total of three loads, but you can put 4 processors in the system. Note that these trace routers could be somewhat longer, because there are 4 processors in the system, so its is important to keep the number of loads per bus equal to 3.
So, which device becomes boot strap device, will depend on how many processors are installed and which socket they are installed into. When the system powers up each processor arbitrates with the chipset to see which core is Core 0, the boot strap device. With the time you could change the system configuration. However, the boot strap device has to be the earliest revision of the processor. So if there is A1 and B1 processor in the system, then the A1 has to be the boot strap device because the OS will assume that all other processors in that system have the same feature capabilities as the boot strap device. Every time the BIOS will basically be checking other processor versions and reassigning the boot strap device to the earlier version if necessary.